A data processing system includes a central processing unit (CPU) that executes instructions and thereby manipulates data. The instructions and data are stored in a memory system, which is typically isolated from the CPU. The CPU interacts with the memory system through a memory interface. The functioning of the memory interface is predominantly under the control of the CPU, and is typically performed by a memory controller. The memory controller can be integrated tightly with the CPU, such as on the same silicon chip as the CPU, or it can be included with other components of the data processing system, one such component often referred to as a north-bridge chip.
There are many types of memory. One type is referred to as dynamic random access memory (DRAM). A DRAM system can include several known types of DRAM, of which double data rate (DDR) is an example. One may refer to the memory controller that governs the interface to the DRAM system as a DRAM controller. Furthermore, one may refer to a memory controller that interfaces a CPU to DDR DRAM as a DDR DRAM controller.
DDR DRAM conforms to industry standard electrical and protocol standards set forth by the Joint Electron Devices Engineering Councils (JEDEC). These standards define how the contents of the DRAM are accessed (read), and stored (written). The original DDR standard has recently been enhanced to include standards known as DDR2 and DDR3. The interface to any of these DDR DRAMs is accomplished primarily through two signal classes, DQ (data) and DQS (data strobe).
The JEDEC standard interface specifies that during a read operation, the DDR DRAM will issue these two signal classes at the same time, a manner commonly referred to as “edge aligned”. In order for the DRAM controller to correctly acquire the data being sent from the DDR DRAM, the DRAM controller typically utilizes a delay-locked loop (DLL) circuit to delay the DQS signal so that it can be used to correctly latch the DQ signals. Topological and electrical difference between DQ, DQS, MEMCLK, and ADDR/CMD interconnects result in timing skew between these signals, making it difficult to establish a proper delay for the DLL.
The DRAM controller is always responsible for driving the main memory clock, designated “MEMCLK”, as well as address and command signals to the memory. Thus during write cycles, the DRAM controller must drive DQ, DQS, and MEMCLK with the proper timing relative to one another. During write cycles, the DDR standard requires that transitions in DQS must be approximately synchronous with transitions in MEMCLK, and transitions in DQ must be centered around transitions in DQS (not edge aligned).
Moreover, memory chips now operate at far higher speeds than the speeds of the original DDR DRAMs. These speeds are now so high that signal propagation delays between the DRAM controller and the memory chips can exceed one MEMCLK cycle. In addition, signal routing used by DDR2 and DDR3 dual in-line memory modules (DIMMs) adds additional skews between these signals. Specifically, DDR3 DIMMs commonly route the MEMCLK and address and command signals to all DRAM chips on a DIMM in sequence using a “fly-by” technique, while at the same time they route the DQ and DQS signals directly to the corresponding memory chip.
All these constraints make it difficult for DRAM controllers to launch the DQ, DQS, and MEMCLK signals so that they arrive at the memory chips on the DIMM with proper timing.